1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to mask-programmed read-only memory (mask-ROM).
2. Prior Arts
Three-dimensional mask-programmed read-only memory (3D-MPROM) has the potential to replace DVD and Blu-Ray Discs. It is ideal for mass publication. U.S. Pat. No. 5,835,396 discloses a 3D-MPROM. It is a monolithic semiconductor memory. As illustrated in FIG. 1, a typical 3D-MPROM comprises a semiconductor substrate 0 and a 3-D stack 10 stacked above. The 3-D stack 10 comprises M (M≥2) vertically stacked memory levels (e.g. 10A, 10B). Each memory level (e.g. 10A) comprises a plurality of upper address lines (e.g. 2a), lower address lines (e.g. 1a) and memory cells (e.g. 5aa). Each memory cell stores n (n≥1) bits. Memory levels (e.g. 10A, 10B) are coupled to the substrate 0 through contact vias (e.g. 1av, 1av′). The substrate circuit 0X in the substrate 0 comprises a peripheral circuit for the 3-D stack 10. Hereinafter, ×M×n 3D-MPROM denotes a 3D-MPROM comprising M memory levels with n bits-per-cell (bpc).
3D-MPROM is a diode-based cross-point memory. Each memory cell (e.g. 5aa) typically comprises a diode 3d. The diode 3d can be broadly interpreted as any device whose electrical resistance at the read voltage is lower than that when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. Each memory level (e.g. 10A) further comprises at least a data-coding layer (e.g. 6A). The pattern in the data-coding layer is a data-pattern and it represents the digital data stored in the data-coding layer. In this figure, the data-coding layer 6A is a blocking dielectric 3b, which blocks the current flow between the upper and lower address lines. Absence or existence of a data-opening (e.g. 6ca) in the blocking dielectric 3b indicates the state of a memory cell (e.g. 5ca).
In prior arts, data-patterns for different memory levels are transferred from separate data-masks. Pattern-transfer is also referred to as “print”, transfers a data pattern from a data-mask to a data-coding layer. Hereinafter, “mask” can be broadly interpreted as any apparatus that carries the source image of the data to be printed. FIGS. 2A-2B illustrate two prior-art data-masks 4A, 4B. Each data-mask (e.g. 4A) is comprised of an array of mask cells “aa”-“bd”. The mask-pattern (clear or dark) at each mask cell determines the existence or absence of a data-opening at the corresponding memory cell. For example, the mask-opening 4ca on the data-mask 4A leads to a data-opening 6ca at cell 5ca of the memory level 10A; the mask-openings 4′aa, 4′da on the data-mask 4B lead to data-openings 6′aa, 6′da at cells 5′aa, 5′da of the memory level 10B.
To further increase storage density, 3D-MPROM can store n (n>1) bits-per-cell (bpc). U.S. patent application Ser. No. 12/785,621 discloses a large-bpc 3D-MPROM. As illustrated in FIG. 3, each memory cell (e.g. 5aa) stores two bits: Bit-1 and Bit-2. Bit-1 is physically implemented by an extra implant, while Bit-2 is physically implemented by a resistive layer 3r. Hereinafter, j-th bit-in-a-cell denotes the j-th bit stored in an n-bpc cell (n≥j). For example, the 1st bit-in-a-cell in a 2-bpc cell is Bit-1; the 2nd bit-in-a-cell in a 2-bpc cell is Bit-2.
In prior arts, the data-patterns for different bits-in-a-cell (e.g. Bit-1, Bit-2) are printed from separate data-masks. FIGS. 4A-4B illustrate two prior-art data-masks 4C, 4D. Each data-mask (e.g. 4C) is comprised of an array of mask cells “aa”-“bd”. The mask-pattern (clear or dark) at each mask cell determines the existence or absence of the extra implant or the resistive layer at the corresponding memory cell. For example, the mask-opening 4xa* on the data-mask 4C leads to the extra-implanted layer 3i at cells 5ca, 5da; the mask-openings 4′ba*, 4′da* on the data-mask 4D lead to the removal of the resistive layer 3r at cells 5ba, 5da. 
Prior arts generally require M×n data-masks for an ×M×n 3D-MPROM, because each memory level and each bit-in-a-cell need a separate data-mask. At 22nm node, each data-mask costs ˜$250 k (hereinafter, k=1,000). Accordingly, the data-mask set of an ×8×2 3D-MPROM, including 16 (=8×2) data-masks, will cost ˜$4 million. This high data-mask cost will hinder widespread applications of the 3D-MPROM. To lower the data-mask cost, the present invention discloses a three-dimensional offset-printed memory (3D-oP).